Chip design has never been more economically important. Yet in an $800 billion industry, it still depends on scarce experts and thousands of manual engineering hours for every chip.

It is also one of the few domains that grades its own work. Simulators test whether a design is correct. Regressions identify what broke. Timing, power, area, and sign-off tools return concrete results at every stage of the flow.

Chip design is therefore one of the first high-value domains where recursive self-improvement can become practical. The evaluation signals agents need to learn from their own work are continuously produced by tools that every design team already runs. What has been missing is a system that closes the loop across the full design flow.

Agentrys is building this closed-loop system across the EDA stack. The company has raised $24.5 million in total funding, comprising an oversubscribed $19.1 million seed round that we led and a prior $5.4 million pre-seed led by MediaTek. We’re proud to partner with Mark Ren and the Agentrys team as they build a self-improving engineering workforce for chip design.

From workflow to workforce

Agentrys is defining a new category, Agentic Design Automation (ADA): the move from tools that automate individual tasks to intelligent systems that automate, learn from, and continuously improve entire engineering workflows.

Two choices in the design of the platform matter most to us.

First, the platform is open. Customers build their own agents on Agentrys and connect them to commercial EDA products, internal tools, and existing infrastructure. Those agents, and the knowledge they accumulate, remain under the customer’s control. Chip designs and failure histories are among a semiconductor company’s most sensitive assets, so any system that learns from that data must do so inside the customer’s environment.

Second, the design intelligence layer learns continuously from each customer’s usage and evaluation signals. Agent-native tools and custom models extend what general-purpose models can do in chip design. Frontier models provide one layer of capability; Agentrys builds the system that connects their outputs to tools, evaluations, and the next engineering decision.

As Mark describes it, each workflow generates engineering observations that are evaluated and fed back into the next run. General-purpose models are increasingly available to every chipmaker. The advantage comes from what the system learns about a specific customer’s methodology, tool behavior, and engineering judgment. That knowledge remains proprietary to the customer and becomes more valuable with use.

Agentrys has already demonstrated the platform end to end: an autonomous multi-agent workflow took a 32-bit CPU from specification to a sign-off-clean GDS layout with no human in the loop. On NVIDIA’s public CVDP verification benchmark, Agentrys is among the first to exceed 90% accuracy, with its agent evolution techniques improving performance over successive iterations.

Its partners include several of the world’s top fabless semiconductor companies, a leading global foundry, and a number of chip startups. Current engagements span end-to-end digital and analog design flows, with system design on the roadmap.

Chip design is naturally verifiable

For decades, electronic design automation tools have automated increasingly sophisticated parts of chip design. Yet the work surrounding those tools remains fragmented across RTL, verification, physical design, analog, and sign-off. Connecting those stages still depends on scarce experts, project-specific scripts, and company-specific flows.

Most AI tools enter this environment as point solutions: generating a block of RTL, diagnosing a test failure, or tuning a tool setting.

Optimizing those tasks in isolation leaves the harder problem untouched. A timing, power, or congestion issue uncovered during physical design may force a microarchitectural change. The RTL must then be updated, the design re-verified and re-implemented, and the results measured again. The unit of work that matters is the complete iteration across the design flow.

Agents become useful when they can operate across that full iteration. An agent can propose a change, carry it through the flow, inspect the results, and use that evidence to decide what to try next. The result is a faster workflow in which each iteration informs the next.

This orchestration layer cuts across incumbent EDA product boundaries. Real design flows combine commercial products from multiple vendors, internal infrastructure, and years of company-specific methodology. No single vendor controls the entire environment.

Why Agentrys

The right domain for self-improvement. Chip design combines enormous economic value, scarce expertise, and objective evaluation at every step. That combination makes it one of the first places recursive self-improvement can move out of research and into production, where being right is settled by whether the silicon works.

A platform that compounds each customer’s advantage. Each customer gets a system that learns its design methodology and improves from its own evaluation signals. The agents built on the platform remain under that customer’s control, as does the knowledge they accumulate. The underlying models are broadly available; the customer-specific capabilities built through repeated use are not. That distinction matters in procurement as much as it does in performance.

Deep experience across EDA and AI. Mark has spent nearly three decades in EDA and AI R&D at NVIDIA Research and IBM Research. At NVIDIA, he led ChipNeMo, the first industrial large language model for chip design. The team includes researchers and engineers from NVIDIA, Meta, AMD, Samsung, Google, and Siemens. Its members helped create ChipNeMo, NVCell, DREAMPlace, VerilogEval, and CVDP, along with production EDA tools and design infrastructure.

In our conversations, they moved fluently between model research and the systems work required to carry a design through sign-off.

The ambition

Agentrys’ long-term vision extends beyond automating today’s design flow. It is building engineering systems that carry learning from one design to the next and take on more complex work over time. Over time, these systems could take on more of the workflows that determine whether chips ship on time and meet their functional and performance targets.

If Agentrys succeeds, design methodology will no longer be encoded piecemeal in expert memory, project-specific scripts, and informal handoffs. It will become a reusable system that preserves what a team learns from each design and applies it to the next.

We believe this learning layer will become a core part of the next generation of EDA. Agentrys is building it in a way that keeps each customer in control of the knowledge the system accumulates on its behalf. We are proud to back Mark and the team.

Read Agentrys' announcement.